Abstract
This paper investigates the use of reconfigurable computing and readily available Field Programmable Gate Array (FPGA) platforms to expedite the generation of input-patterns for testing integrated circuits after manufacture. Unlike traditional fault simulation approaches, our approach emulates single stuckat fault behavior in a circuit and finds the minimum test pattern set to detect it. In this paper, we present a method to insert faults into a circuit netlist by identifying circuit fault sites. We then present our parallel method of fault emulation and describe our method to organize and compress the input patterns needed to identify all faults. Using circuits from the ISCAS and MCNC benchmark suites, we show that our approach does better than a commercial tool in test-set reduction. Index Terms-Field Programmable Gate Arrays, Reconfigurable Computing, Fault emulation, stuck-at-faults, manufacturing defect, test pattern generation, test-set compression.