Abstract
Conference Title: 2016 IEEE 25th North Atlantic Test Workshop (NATW) Conference Start Date: 2016, May 9 Conference End Date: 2016, May 11 Conference Location: RI, USA We propose an architecture for an FPGA-based tester for a 3D stacked IC. Our design exploits the underlying structure of the FPGA, allowing it to be used to efficiently store and apply predefined test patterns at a high bandwidth, reducing the FPGA resources required and often reducing scan shift toggling. The proposed approach and its advantages can generally also be applied to 2.5D multi-die circuits containing FPGAs.