Abstract
As technology scales and the geometries of the transistors shrink, leakage current and subsequently total power consumption increase considerably. Many of the benefits brought forth by the smaller transistors will be lost if the high power consumption problem cannot be solved. The leakage power consumption problem is especially relevant to an FPGA because of the amount of unused interconnect and logic fabric in the chip during any operation. In this paper, we propose to lower the power consumption of a standard SRAM based FPGA by using half-width transistor stacks and adaptive body biasing techniques. SPICE simulation on a standard pass-transistor based switch block and a switch matrix from the Xilinx XC4000 FPGA show that the leakage power can be reduced by up to 46% for a 45nm technology node and up to 10% for a 70nm technology node when a switch-matrix is loaded.