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Enhancing online error detection through area-efficient multi-site implications
Conference proceeding

Enhancing online error detection through area-efficient multi-site implications

N Alves, Y Shi, J Dworak, R I Bahar, K Nepal and IEEE Computer Soc
29th VLSI Test Symposium, pp.241-246
05/2011
DOI: https://doi.org/10.1109/VTS.2011.5783728

Abstract

Benchmark testing Delay Electrical fault detection Hardware Integrated circuit modeling Logic gates
We present a new method to identify multi-site implications that can significantly increase the fault coverage of error-detecting hardware without increasing the area overhead. This method intelligently divides the input space about the functions of internal circuit sites and finds new valuable implications that can share gates in checker logic.

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