Abstract
While 3D integrated circuits provide many security advantages, one disadvantage is the insertion of a Trojan die into the stack. In this paper, we explore a technique to detect an extra die through delay analysis.
- Title
- Detecting a Trojan Die in 3D Stacked Integrated Circuits
- Author/Creator
- Soha Alhelaly - Southern Methodist UniversityJennifer Dworak - Southern Methodist UniversityTheodore Manikas - Southern Methodist UniversityPing Gui - Southern Methodist UniversityKundan Nepal - University of St. Thomas - MinnesotaAlfred L. Crouch - SiliconAid Solut, Cedar Pk, TX USAIEEE
- Publication Details
- 2017 IEEE 26TH NORTH ATLANTIC TEST WORKSHOP (NATW)
- Publisher
- IEEE
- Number of pages
- 6
- Grant note
- CCF-1061164 / NSF; National Science Foundation (NSF)
- Academic Unit
- Electrical & Computer Engineering
- Language
- English
- Resource Type
- Conference proceeding
- Record Identifier
- 991015164159803691