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Cache-Friendly Bitmap Compression on Symmetric Multiprocessors
Conference proceeding

Cache-Friendly Bitmap Compression on Symmetric Multiprocessors

Alexia Ingerson, David Chiu and Jason Sawin
2017 IEEE International Conference on Autonomic Computing (ICAC), pp.71-72
07/2017
DOI: https://doi.org/10.1109/ICAC.2017.23

Abstract

bitmap compression block size cache friendly Computational modeling Conferences Indexing Instruction sets Phasor measurement units Synchronization Voltage measurement
A worksharing model is presented to enhance parallel compression of data-intensive bitmap indices. To increase spatial locality, our approach interleaves multiple independent bitmaps in a combined file. Each file block, which fits entirely in cache, is processed by independent threads. Results show that our model significantly outperforms embarrassingly-parallel designs.

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