Abstract
As devices and operating voltages are scaled down, future circuits will be plagued by higher soft error rates, reduced noise margins and defective devices. A key challenge for the future is retaining high reliability in the presence of faulty devices and noise. Probabilistic computing offers one possible approach, whether computing is completely CMOS-based or not. In this work, we will describe our approach for mapping circuits onto CMOS using principles of probabilistic computation. In particular, we demonstrate how Markov random field elements may be built in CMOS and used to design combinational and sequential circuits running at ultra low supply voltages. We show that with our new design strategy, circuits can operate in highly noisy conditions and provide superior noise immunity, at reduced power dissipation. While the experimental work is all CMOS-based, our approach could prove essential for any alternative digital logic technology, since defective devices, noise, and restricted power supplies are unavoidable constraints for all envisioned alternatives at the end of the CMOS roadmap.